PEC Etching of Intrinsic Silicon

Introduction & Motivation for Infrared Photonics

In short: silicon chips are great at handling near-infrared light, but nobody’s pushed them hard into the mid-infrared range where you can chemically “fingerprint” a gas or liquid. Porous silicon can get there — if you can actually etch it, which turns out to be the hard part for the specific wafers this thesis needed.

Most silicon photonics work targets near-infrared data links. The $2\text{–}12\ \mu\text{m}$ mid-infrared band gets far less attention, even though it’s the range spectrometers use for chemical detection. Silicon is a natural fit: cheap, and already integrated at scale.

Porous silicon is the key material here. Etch away part of the silicon and its refractive index becomes tunable anywhere from $1.1$ to $3.0$, instead of bulk silicon’s fixed $3.5$ — enough range to build high-contrast optical structures in a single material.

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The Intrinsic Silicon Porosification Challenge

In short: the silicon this thesis needed to etch barely conducts, and etching needs conductivity. So I had to give it some, artificially, without changing the material itself.

Porous silicon usually starts from doped wafers, because electrochemical etching consumes positive charge carriers (holes):

$Si + 6\text{ HF} + h^+ \longrightarrow \text{SiF}_6^{2-} + H_2 + 4\text{ H}^+ + e^-$

Intrinsic silicon (i-Si) has almost no free carriers of its own ($n_i \approx 1.07 \times 10^{10}\ \text{cm}^{-3}$), so it runs out of holes almost instantly and barely etches at all.

My fix: bond a heavily-doped $p^{++}$ carrier wafer onto the i-Si. Under light and a positive bias, holes diffuse out of the $p^{++}$ layer and into the i-Si — supplying, from the outside, the carriers the intrinsic silicon doesn’t have on its own.

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Ohmic Contact Metallurgy & Sintering

In short: the bond between the two wafers needs a clean electrical path, or the etch would waste energy as heat instead of removing silicon.

I used a $25/400\text{ nm}$ Ti/Al metal stack to connect the two wafers electrically. A poor contact here means voltage spikes and wasted heat during etching instead of clean current flow.

Annealing at $400^\circ\text{C}$ makes the titanium react with the silicon underneath it, forming titanium silicide — a solid, low-resistance electrical weld between the metal and the wafer:

$\text{Ti} + 2\text{ Si} \longrightarrow \text{TiSi}_2$

The leftover titanium isn’t wasted either: because $\text{TiO}_2$ forms more readily than $\text{SiO}_2$ ($-225.5$ vs. $-217.7$ kcal/mol), any unreacted titanium mops up native oxide at the interface before it can get in the way.

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Process Flow

The complete cleanroom fabrication flow developed for senior thesis work is outlined below:

[Degrease Wafers] 
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[O2 Descum (150W, 1 min)] 
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[1-min HF Dip (Native Oxide Removal)] 
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[E-Beam Deposition (25/400 nm Ti/Al)] 
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[Hand Cleave into Four Quarters] 
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[O2 Plasma Activation (0.4 mbar, 75-100W)] 
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[SUSS Vacuum Wafer Bonding (400 °C)] 
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[Post-Bond Anneal (400 °C, 30 mins)]