CMOS Integrated Circuit Wafer Fabrication & Metrology

From Bare Silicon to Functional Integrated Circuits

In short: I built working transistors, diodes, and capacitors on a bare silicon wafer by hand, in a real cleanroom, then measured how well they actually worked.

In ECE 444 (Theory and Fabrication of Integrated Circuits) at UIUC, I fabricated a silicon wafer containing planar MOSFETs, lateral BJTs, pn-junction diodes, and MOS capacitors from scratch in a Class 100/1000 cleanroom — the same device types inside every real chip, built one wafer at a time instead of by the billion.

Fabrication used a 5-mask photolithographic process: diffusion, gate oxidation, etching, and aluminum metallization. Afterward I measured every device electrically and compared the results back to the process — where a mask undercut, where diffusion spread sideways more than planned, where parasitic resistance crept in.

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Cleanroom Fabrication Process Flow

Every structure on the wafer came from the same five-mask sequence, built up layer by layer:

1. Oxidation: RCA clean, then grow a thick field oxide over the whole wafer.
2. Mask 1 — Deep p-type wells: Open the mask, etch through the oxide, then diffuse boron in deep (15 min predeposition + 45 min drive-in).
3. Mask 2 — Shallow n-type wells: Diffuse phosphorus in shallow, no drive-in, for a sharp junction.
4. Mask 3 — Gate oxide: Strip the oxide over the channel, regrow a thin 250 Å dielectric.
5. Masks 4 & 5 — Contacts and metal: Open contact vias, evaporate aluminum, pattern it, then sinter in forming gas.

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Transconductance & Channel Length Discrepancy ($\Delta L$) Analysis

In short: the transistor’s real channel is shorter than what I drew in CAD, because dopants and etching both eat sideways into it. Draw the channel too short and the two ends touch underground, killing the transistor.

Dopants diffuse sideways under the gate mask, and the BOE etch undercuts the oxide the same way, so the real (metallurgical) channel length is always shorter than the CAD length: $L_{\text{actual}} = L_{\text{CAD}} - \Delta L$. If that shrinkage $\Delta L$ ever equals or exceeds the drawn length, the source and drain regions meet underneath the gate — a punch-through short with no gate control left at all.

On my wafer, the shortest device that still worked had $L_{\text{CAD}} = 10\ \mu\text{m}$, so $\Delta L$ has to sit somewhere between about $8$ and $10\ \mu\text{m}$.

I extracted the exact value from a measurement that doesn’t need to know the gate bias or threshold voltage: comparing the saturation transconductance $g_m$ of a long-channel and a short-channel pMOSFET side by side.

$I_{D,\text{sat}} = \frac{1}{2}\mu_p C_{\text{ox}} \frac{W}{L - \Delta L}(V_G - V_T)^2$

$g_{m,\text{sat}} = \frac{\partial I_{D,\text{sat}}}{\partial V_G} = \mu_p C_{\text{ox}} \frac{W}{L - \Delta L}(V_G - V_T)$

The trick: take the ratio of the two devices’ transconductance slopes ($\text{slope} = \frac{\partial g_m}{\partial V_G}$). Mobility and oxide capacitance are the same for both devices, so they cancel out of the ratio, leaving an equation with only $\Delta L$ unknown:

$\frac{\text{slope}_{\text{large}}}{\text{slope}_{\text{short}}} = \frac{L_{\text{short}} - \Delta L}{L_{\text{large}} - \Delta L} \implies \Delta L = \frac{\text{slope}_{\text{short}}L_{\text{short}} - \text{slope}_{\text{large}}L_{\text{large}}}{\text{slope}_{\text{short}} - \text{slope}_{\text{large}}}$

Solving it with the measured data gave $\Delta L = 9.97\ \mu\text{m}$ — almost exactly the $10\ \mu\text{m}$ cutoff where devices stopped working. That’s not a coincidence: it’s the whole explanation for why nothing shorter survived.

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Diode Forward Characteristics & Ideality Factor ($n$)

In short: a real diode isn’t a perfect diode. Two effects blur its textbook I-V curve, and I had to correct for one of them before the underlying physics was visible.

The base-collector diffused diodes follow the standard junction equation:

$I = I_0 \left( \exp\left(\frac{qV_{\text{junction}}}{n k T}\right) - 1 \right)$

Correcting for Series Resistance ($R_s$)

Plotted against the raw terminal voltage, the ideality factor $n$ looks distorted at both ends: leakage dominates at low voltage, and series resistance ($R_s$) chokes off current at high voltage. Neither is the diode’s real behavior.

$R_s$ is fixable: pull it from the linear slope of the forward I-V curve at high current, then subtract its voltage drop back out:

$V_{\text{junction}} = V_{\text{measured}} - I \cdot R_s$

Once corrected, the curve makes sense: $n$ climbs from recombination at low bias, levels off around $n \approx 2.7$, then drops again at high forward current.

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MOS Capacitor $C$-$V$ Profiling & Substrate Characterization

In short: sweeping voltage across a tiny capacitor and watching its capacitance change reveals how good the oxide is and how heavily the silicon underneath is doped — without needing to cut the wafer open.

I swept three circular MOS capacitors ($r = 150\ \mu\text{m}$) from accumulation to inversion to pull out oxide integrity, flatband voltage, and substrate doping:

Parameter Extraction

At strong inversion, the oxide capacitance and the silicon’s own depletion-layer capacitance act like two capacitors in series ($C_{\text{min}}^{-1} = C_{\text{ox}}^{-1} + C_d^{-1}$). Solving that for the depletion capacitance gives the maximum depletion width $w_m$, and from there the substrate’s actual donor concentration $N_d$:

$w_m = \frac{\epsilon_{\text{Si}} A}{C_d}, \quad N_d = \frac{2 \epsilon_{\text{Si}} \phi_s}{q w_m^2}$

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Dielectric Breakdown Analysis

In short: the oxide on this particular test wafer was almost 6× thicker than intended, and that single fact explains why its breakdown field looked so much weaker than a fresh gate oxide’s should.

Breakdown field is just $E_{\text{bd}} = V_{\text{bd}} / t_{\text{ox}}$ — voltage where the oxide fails, divided by how thick it is. I compared two ways of getting $t_{\text{ox}}$:

The measured thickness (1402 Å) is nearly 6× the 250 Å the dry-oxidation growth curve predicted. That gap — native oxide buildup and interface traps on an aged test wafer — is what dragged the breakdown field down from the ~7.2 MV/cm a fresh thermal oxide should hold.

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Takeaways

Channel shortening this close to the drawn length ($\Delta L \approx 9.97\ \mu\text{m}$ against a $10\ \mu\text{m}$ device) is why modern CMOS nodes need self-aligned gates — at this scale, lateral diffusion alone can kill a transistor. Threshold voltages pulled from the MOS capacitors clustered more tightly than the ones extrapolated from FET $g_m$ curves, a reminder that interface traps and contact resistance quietly bias four-terminal parameter extraction.